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Embedded software development process

Exploring the Embedded Software Development Process

An embedded software development process is an evidence-producing lifecycle, not a straight path from requirements to code. Teams repeatedly connect product intent, hardware constraints, architecture, implementation, integration, verification, release and field feedback, and scale the rigor to the risk of the product.

Key takeaways

  • Lifecycle: 9 connected phases run from discovery to operations, and iteration between them is normal.
  • Requirements: Testable requirements name units, tolerances, failure behavior and a verification method.
  • Testing: Six test layers, from static checks to validation, are weighted by risk.
  • Evidence: Reproducible builds, traceability and recorded results make a release attributable.
  • Dev Station: Dev Station runs this process for embedded and IoT teams in the US and UK.

What should a team decide before estimating embedded software?

Before estimating, a team should frame the system: product intent, system boundary, constraints and an evidence plan that grows with the design.

Product intent

Describe users, operating scenarios, hazards, misuse, environment, service life, manufacturing volume assumptions, and what success means at system level.

System boundary

Identify sensors, actuators, processors, radios, power, cloud services, mobile apps, manufacturing systems, accessories, and external dependencies.

Constraints

Capture timing, memory, energy, boot, thermal, cost, availability, cybersecurity, privacy, safety, regulatory, and maintenance constraints.

Evidence plan

Decide what reviews, analyses, tests, traceability, records, and approvals will demonstrate the product is ready. Evidence should grow with the design, not be reconstructed at release.

What are the phases of embedded software development?

Embedded software development runs through nine connected phases, from discovery and feasibility to operations and maintenance, with iteration expected between them.

Iteration is expected. A failed timing test may change architecture; a component shortage may change hardware; a threat analysis may alter boot and update design. Configuration control keeps these loops understandable.

01

Discovery and feasibility

Resolve the riskiest assumptions with datasheet analysis, prototypes, measurements, regulatory research, supplier checks, and architecture options. Label prototype code clearly.

02

Requirements

Write testable system and software requirements with rationale, source, priority, units, tolerances, failure behavior, and verification method.

03

Architecture

Partition hardware and software; define execution contexts, interfaces, data flows, timing, memory, power states, trust boundaries, diagnostics, and update strategy.

04

Detailed design

Specify state machines, task priorities, buffers, persistence, driver contracts, error handling, algorithms, configuration, and test seams.

05

Implementation

Apply coding standards, review, static analysis, unit tests, dependency controls, secure practices, and small integrations against known hardware revisions.

06

Integration

Bring up boot stages, clocks, memory, peripherals, RTOS or OS, middleware, applications, and external systems in a planned order with observable checkpoints.

07

Verification and validation

Prove requirements, interfaces, reliability, performance, safety and security controls; then confirm the integrated product supports intended use in representative conditions.

08

Release and production transfer

Freeze controlled inputs, reproduce artifacts, approve known issues, provision identities and keys, support factory test, and preserve release evidence.

09

Operations and maintenance

Monitor field health, triage incidents, manage vulnerabilities and dependencies, issue recoverable updates, support variants, and plan end of support.

How do you make embedded requirements measurable?

Replace vague statements with defined conditions, thresholds and a verification method, as the table below shows.

Weak statement Stronger direction Verification idea
The device starts quickly Define power condition, hardware revision, readiness event, maximum time, and measurement point Automated power-cycle timing across voltage and temperature conditions
The battery lasts a long time Define battery, duty cycle, radio conditions, operating profile, shelf time, and end threshold State-level current measurements plus representative-duration testing and model
Communications are secure Name assets, attackers, interfaces, authentication, confidentiality, integrity, replay, key lifecycle, and update duties Threat-linked tests, protocol review, key and update failure tests
Errors are handled List detectable faults, safe or degraded response, retries, logging, user indication, recovery, and persistence Fault injection with expected state and diagnostic evidence

Traceability links the evidence

A useful trace links stakeholder need to system and software requirements, design, code or configuration, tests, results, anomalies, and release. It helps impact analysis; it should not become paperwork detached from engineering.

Which cross-cutting concerns need early decisions?

Timing, memory, power, safety, security and maintainability need early decisions, because each constrains architecture and is expensive to change late.

Timing and concurrency

Budget deadlines, interrupt latency, task execution, blocking, bus contention, priority inversion, jitter, and overload behavior. Measure on representative targets.

Memory and storage

Budget flash, RAM, stacks, heaps, buffers, logs, filesystems, update slots, wear, corruption recovery, and growth margin by variant.

Power and thermal

Define states, wake sources, sequencing, peripheral leakage, radio retries, clock strategy, thermal throttling, and measurement points.

Safety and resilience

Analyze hazardous behavior, single points of failure, watchdog strategy, brownout, sensor plausibility, actuator defaults, fault containment, and recovery.

Security and privacy

Model assets and threats; design identity, secure boot, debug access, least privilege, encrypted transport, protected storage, logging, updates, and decommissioning.

Maintainability

Plan diagnostics, telemetry, feature flags where safe, compatibility, manufacturing mode, service tools, component replacement, and support documentation.

How should a team bring up an embedded system?

Bring it up in observable slices, one diagnosable path at a time, with a compatibility matrix and a board bring-up checklist.

  • Maintain a hardware to software compatibility matrix covering boards, BOM substitutions, bootloader, programmable logic, radio, OS, application, and calibration.
  • Create a board bring-up checklist for rails, reset, clocks, debug, memory, console, storage, buses, network, sensors, actuators, low-power states, and production interfaces.
  • Use stable test doubles and simulators for unavailable hardware, while preserving tests on real boards for electrical, timing, radio, power, and peripheral behavior.
  • Integrate one diagnosable path at a time. A heartbeat, console, reset reason, and traceable build identifier shorten fault isolation.
  • Record bench setup, instrument configuration, firmware version, hardware revision, environmental condition, and raw evidence for failures.
  • Keep exploratory patches out of release branches until reviewed, tested, and connected to a tracked change.

How should embedded testing be layered?

Layer tests around risk, from static analysis and unit tests up to system tests and validation in representative conditions.

Layer Primary purpose Representative methods
Static Find defects without execution Review, compiler warnings, static analysis, dependency and configuration scans
Unit Check isolated logic and boundaries Host or target tests, mocks, property and boundary tests
Component Exercise drivers, services, and protocols Target tests, peripheral fixtures, protocol simulators
Integration Check interfaces and interactions Hardware-in-loop, network and backend test environments, fault injection
System Verify product requirements Environmental, performance, power, EMC-related prechecks, endurance and recovery tests
Validation Assess intended use and workflow Representative users, scenarios, environments, and operational procedures

Test the negative space

Include malformed inputs, noisy sensors, stalled buses, full storage, low voltage, reset during update, unavailable time source, duplicate messages, expired credentials, network loss, overload, and repeated recovery. Many field defects live outside the nominal path.

How do you make embedded release artifacts attributable?

Build through controlled automation so that version, source, configuration and toolchain tie to each binary, and keep a tested recovery path for interrupted updates.

01

Create a candidate

Build through controlled automation from reviewed source and configuration. Generate hashes, version metadata, dependency inventory, and release notes.

02

Verify the candidate

Run the defined suite against the exact artifacts on supported hardware variants. Preserve results and deviations.

03

Review readiness

Assess unresolved anomalies, cybersecurity findings, production dependencies, documentation, support training, rollback, and approvals.

04

Protect and publish

Apply signing and access controls, store artifacts immutably, transfer only through authorized channels, and verify installation.

05

Monitor rollout

Use staged deployment when possible, define stop conditions, observe device health, and keep a tested recovery route.

How should embedded teams use development metrics?

Treat each metric as a question to investigate and not as a target to hit.

Change failure pattern

Which components repeatedly regress, and are interfaces, tests, ownership, or hardware stability responsible?

Requirements coverage

Are critical behaviors linked to objective evidence, and are uncovered items understood rather than hidden in a percentage?

Build health

Can the team build, flash, provision, test, and identify supported variants without tribal knowledge?

Defect escape

What escaped, why did existing controls miss it, and which prevention or detection change is proportionate?

Resource margin

How are timing, memory, CPU, storage, power, and network margins trending across releases?

Field observability

Can support distinguish hardware, configuration, network, update, and application faults without exposing sensitive data?

Frequently asked questions

Five questions come up most often on this topic.

Is waterfall or agile better for embedded products?

Neither label is sufficient. Hardware lead times and assurance gates require planning, while technical learning requires iteration, so use short evidence-producing increments inside controlled system milestones.

When should testing begin?

During framing and architecture. Define verification with the requirements, build test seams into the design, and automate at the lowest practical layer before full hardware integration.

Can prototype code become production code?

Only after it meets production requirements for architecture, review, error handling, concurrency, security, tests, documentation, licensing and maintainability. Prototype success shows feasibility, not release readiness.

What is traceability for in embedded projects?

Traceability links a stakeholder need to requirements, design, code, tests, results and release, so a team can assess the impact of a change. It supports impact analysis and should not turn into paperwork.

Why test the negative space?

Many field defects sit outside the nominal path, so tests should include malformed inputs, stalled buses, full storage, low voltage, reset during update and network loss.

Dev Station Technology runs the embedded development lifecycle for hardware and IoT teams, from architecture and firmware to verification, release and field operations. Device and telemetry data stays in your own cloud tenant, in the region your policy requires. Where a client needs SOC 2, HIPAA or UK GDPR evidence, we build the technical controls those frameworks ask for and work alongside the assessor who issues the certificate. Our engineers work from Vietnam with overlap into US Eastern, US Pacific and UK GMT hours, and we invoice in USD or GBP.

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